A High Speed Dynamic Logic Circuit Design With Low Propagation Delay And Leakage Power For Wide Fan-In Gates
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Date
2022-04
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Department of Electrical and Electronic Engineering
Abstract
Dynamic logic circuits are used in higher-functioning circuit applications due to their speed. Once the static logic circuit was used. But it requires a large number of transis tors, resulting in a large overhead area and high power consumption. So it is replaced by dynamic logic, which has impressive performance compared to static logic. Dynamic logic circuits are employed in a variety of fields, including microprocessors and dynamic memory, because they are faster and have fewer transistors than static logic circuits. However, it has the leakage power and propagation delay issue, which means it won’t be able to demonstrate the necessary performance during the evaluation phase. Wide fan-in domino gates are more compact, resulting in more sub-threshold leakage current channels. When the PDN is OFF, noise from any source comes at gates and develops a gate to source voltage. It also increases the leakage power and propagation delay. As a result, reducing the leakage power and propagation delay while designing a dynamic logic circuit is a major issue. A novel dynamic logic model with low leakage power and propagation delay in contrast to previous models, is developed by adding delay compo nents and changing stacking effect circuitry. Increased sub-threshold leakage current is one of the primary causes of leakage power rise. Sub-threshold conduction or leakage current is the current that flows between the source and drain of a MOSFET when the transistor is in the sub-threshold region, or weak-inversion region for gate-to-source volt ages less than the threshold voltage. When the size of a technical feature is reduced, the supply voltage and threshold voltage are reduced as well. As the threshold voltage drops, the leakage current grows exponentially thus increasing the sub-threshold leakage power. The LTSpice tool is used to illustrate the robustness of the proposed model uti lizing 45nm PTM technology for OR-AND logic gate functionality and various supply voltages. Simulation results show a good percentage of improvement in both leakage power and propagation delay.
Description
submitted by Md. Maharaj
Kabir, bearing Matric ID. ET181018 and Fahim Abrar, bearing Matric ID. ET181024
of session Autumn 2021