Grid Connected Micro¬grid Fault Current Reduction Using Non¬superconducting Fault Current Limiter
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Date
2020-12
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Department of Electrical and Electronic Engineering
Abstract
Integration of renewable energy sources are increasing very fast in the existing conven tional energy sources because of the environmental concerns worldwide. Along with the increasing use of renewable energy sources localized generation of electricity using renewable energy sources which are widely known as micro-grid have also increased ex ponentially over the last few years. Although this is a very important step toward green energy but it comes with an enormous challenges of maintaining power quality, ensuring stability and reliability of system as well as protecting the system against high magnitude of fault current during faults in the presence of a large number of distributed generation (DG) sources. This high magnitude of fault current needs to be taken into consideration while designing protection for any system. In this thesis, we have used a non super conducting fault current limiter (NSFCL) for a grid connected micro-grid to mitigate the fault current of the micro-grid . The micro-grid consists of a photovoltaic (PV) solar farm and a Biomass based DG. The PV system has been controlled in one stage, MPPT output is directly fed to the controller to generate gate pulse for the inverter. Both voltage and current control mode is used to control the DG. Voltage control mode generates reference current for the current controller which then possessed with PI controller to generate gate pulse for the inverter. Two NSFCLs are added after inverter to protect DGs against high level of fault current. Fault sensing circuitry is added at the grid side based on the RMS value of per phase voltage. Three line to neutral (3LN) and two line to neutral (2LN) faults are applied in the micro-grid to see the response of the DGs in the presence and absence of NSFCL. We have used Matlab/Simulink to carry out the simulation. Our sim ulation results show a good percentage of improvement in fault current mitigation in both DG.
Description
submitted by Nurul Mostafa Tarek,
bearing Matric ID. ET161054 and Aynul Farid Bin Rahim, bearing Matric ID. ET161052
of session Spring 2020