Design of an universal numeric segmented display and implementation of its decoder circuit in FPGA

dc.contributor.authorKader, M.A.
dc.contributor.authorHossain, Kazi Sahadat
dc.contributor.authorMunir, Mohammad Serajum
dc.contributor.authorDhar, Rajvi Sutra
dc.contributor.authorRahaman, Md. Arifur
dc.date.accessioned2019-01-18T11:23:33Z
dc.date.available2019-01-18T11:23:33Z
dc.date.issued2016-10-28
dc.description.abstractSegment display is very important in displaying numeric data. Although matrix display can be used to show any number with better font but it has some major disadvantages compared to segment display. Matrix display uses scanning techniques to show something, this technique is complex to implement and needs more memory. Here, a 20-segment display is proposed which can show numbers and mathematical symbols of 14 different languages. Also a decoder circuit is proposed which takes BCD input and generates output binary combination for 20-segment display of selected language. Finally a prototype of 20-segment display is implemented by LED’s and the decoder circuit is implemented in FPGA. The system is checked for 14 different languages and some mathematical symbols.en_US
dc.identifier.citationICISET2016-ID-76en_US
dc.identifier.isbn978-1-5090-6121-1
dc.identifier.issn978-1-5090-6121-8
dc.identifier.urihttp://dspace.iiuc.ac.bd:8080/xmlui/handle/88203/483
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectFPGAen_US
dc.subjectdecoderen_US
dc.subjectnumeric displayen_US
dc.subjectuniversal numeric displayen_US
dc.titleDesign of an universal numeric segmented display and implementation of its decoder circuit in FPGAen_US
dc.typeArticleen_US

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