Design of an universal numeric segmented display and implementation of its decoder circuit in FPGA
dc.contributor.author | Kader, M.A. | |
dc.contributor.author | Hossain, Kazi Sahadat | |
dc.contributor.author | Munir, Mohammad Serajum | |
dc.contributor.author | Dhar, Rajvi Sutra | |
dc.contributor.author | Rahaman, Md. Arifur | |
dc.date.accessioned | 2019-01-18T11:23:33Z | |
dc.date.available | 2019-01-18T11:23:33Z | |
dc.date.issued | 2016-10-28 | |
dc.description.abstract | Segment display is very important in displaying numeric data. Although matrix display can be used to show any number with better font but it has some major disadvantages compared to segment display. Matrix display uses scanning techniques to show something, this technique is complex to implement and needs more memory. Here, a 20-segment display is proposed which can show numbers and mathematical symbols of 14 different languages. Also a decoder circuit is proposed which takes BCD input and generates output binary combination for 20-segment display of selected language. Finally a prototype of 20-segment display is implemented by LED’s and the decoder circuit is implemented in FPGA. The system is checked for 14 different languages and some mathematical symbols. | en_US |
dc.identifier.citation | ICISET2016-ID-76 | en_US |
dc.identifier.isbn | 978-1-5090-6121-1 | |
dc.identifier.issn | 978-1-5090-6121-8 | |
dc.identifier.uri | http://dspace.iiuc.ac.bd:8080/xmlui/handle/88203/483 | |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | FPGA | en_US |
dc.subject | decoder | en_US |
dc.subject | numeric display | en_US |
dc.subject | universal numeric display | en_US |
dc.title | Design of an universal numeric segmented display and implementation of its decoder circuit in FPGA | en_US |
dc.type | Article | en_US |
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