Design of an universal numeric segmented display and implementation of its decoder circuit in FPGA
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Date
2016-10-28
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE
Abstract
Segment display is very important in displaying
numeric data. Although matrix display can be used to show any
number with better font but it has some major disadvantages
compared to segment display. Matrix display uses scanning
techniques to show something, this technique is complex to
implement and needs more memory. Here, a 20-segment display
is proposed which can show numbers and mathematical symbols
of 14 different languages. Also a decoder circuit is proposed
which takes BCD input and generates output binary combination
for 20-segment display of selected language. Finally a prototype
of 20-segment display is implemented by LED’s and the decoder
circuit is implemented in FPGA. The system is checked for 14
different languages and some mathematical symbols.
Description
Keywords
FPGA, decoder, numeric display, universal numeric display
Citation
ICISET2016-ID-76