Design a 4x4 Multiplier Circuit using Quantum Dot Cellular Automata with Binary Parallel Adder

Abstract

Design a 4x4 Multiplier Circuit using Quantum Dot Cellular Automata with Binary Parallel Adder In Today's world, electronic circuits are being minimized day by day. CMOS technology has reached its peak level, which means transistors size can't be smaller anymore along with power consumption; delay time can't be decreased, and so on. In this case, we suggest an invention of Nano-technology named Quantum-dot Cellular Automata (QCA), another Nano-scale model for substituting traditional Complementary Metal–Oxide Semiconductor (CMOS) innovation. It is a transistor less paradigm by which we can decrease the sudden heat & power density of electronic circuits. This paper presents the 4*4 multiplier design by using a binary parallel adder with QCA. We have achieved a QCA Multiplier in which cell count has been decreased. The cell count of our proposed design is less than 2750 compared to the coplanar multiplier and the delay time is less than 8, and the area is less than 5.5 µm2. It may be utilized in digital signal processing applications and design calculators, mobiles, processors, or image processors that use digital signal processing. QCA Designer 2.3.0 was used to building and test the circuit, and the Coherence vector engine was utilized to simulate it